After being held in France for the first five years, the 2006 MPSoC conference is being moved to the US. The conference will be held in mid-August in Estes Park, Colorado. Registation is now open.

Crescendo Networks is using multiple NIOS II “soft” CPUs in an Altera FPGA in their CN-5000 series “Maestro” platforms. Such “soft multiprocessing” using FPGAs appears to be an emerging trend.

Azul Systems has announced a 48 core device named Vega 2. The cores are 64-bit procesors and the device is expected to contain over 800M transistors. The Vega 2 is expected to be available in 2007.

This week is the Multicore Expo in Santa Clara (see you there).

ClearSpeed has announced that it will participate with AMD, NEC and Sun in what is expected to be Japan’s largest supercomputer. A press release from ClearSpeed describes more about the project.

Both Icera and PicoChip, UK makers of multicore devices, have both recently secured new rounds of funding. Icera has secured an additional $40M, bringing their total to over $80M in funds raised. Last month, PicoChip closed a $20M third round of funding bringing their total company funding to over $40M.

The article Clearspeed Plans AMD Co-processor Link Up in Electronic News mentions that Clearspeed of Bristol, UK is discussing using technology from their CSX 96 core processor as a co-processor for the AMD’s x86 processor line.

In the article Intel Offers Peek into Research Activities Electronic News reports on Intel’s increasing R&D effort, particularly in multicore. A quote from the article:

Now that the company is looking to adding cores in order to scale performance, Intel is now looking at the challenges of putting tens to hundreds of cores on a single chip – such how to do interconnects, feed memory bandwidth and program such chips – and how those issues might be resolved.

Recore Systems has a new reconfigurable computing IP core based on the Chameleon work at the University of Twente in the Netherlands.

Intel announced its new Core Duo paper at CES. It features two mobile optimized cores with special cache sharing features to save power. It also features multiple voltage and clock speeds to select power consumption vs. performance. A white paper is available from Intel.